1. Field of the Invention
The present invention relates in general to computer systems, and more particularly to cache memory systems. Still more particularly, the present invention relates to data cache memory arrays.
2. Description of the Prior Art
Cache memories are used in many computer systems to improve system performance. A cache memory is a relatively small, fast memory which resides between a central processor and main system memory. Whenever the processor reads the contents of a memory location which is stored in the cache memory, the time required to access such location is drastically reduced. A good cache technique can provide a "hit ratio" of well over ninety percent, meaning that no main memory access is necessary for over ninety percent of the read operations performed. Access of data which is stored in the cache memory can improve access times by factors of three to ten times.
A cache performs functions requiring two different types of memory. The first type is the tag memory, or tag RAM, which is used to determine which memory locations are actually stored in the cache memory. The second type of memory is the data cache memory, in which the data is actually stored. In general, the cache tag RAM contains a plurality of entries corresponding to the entries of the data cache. Each entry is indexed by some number of least significant bits of the address generated by the central processor, with the tag entry itself containing the most significant bits of the memory location which is stored in the corresponding data cache entry. If the most significant bits stored in the tag RAM match the most significant bits of the address currently being generated, with the least significant bits of this address acting as an index to the tag RAM, a cache "hit" has occurred and the data to be read may be taken from the corresponding data cache entry. If data corresponding to the desired address is not located in the data cache memory, the tag entry will not match the most significant bits of the address, and a "miss" occurs. This indicates that the data must be retrieved from main system memory and placed into the data cache memory.
When transferring data from a data cache memory and main memory, a cache controller must communicate an address to main memory for each transfer. The cache controller communicates with the main memory over the system bus. At the time when the cache controller needs to communicate with main memory, the system bus may be controlled by other devices. Thus, the cache controller is required to wait until the system bus is available before it can communicate with main memory. This bus contention problem may occur each time the cache controller needs to communicate with the main memory. Due to bus contention, the time required to access memory locations in main memory may be drastically increased.
Furthermore, in multi-processor systems, it is possible to provide each processor in a system with its own cache memory. Each local processor accesses its own cache whenever possible, and accesses main memory through a system bus only when necessary. This situation introduces an important problem known as the "cache coherency problem." The cache coherency problem arises when a single memory location is cached in two or more local caches. If one of the processors writes a new value into that memory location, it will be inconsistent with the value of the same variable, or main memory location, currently cached in the other caches. The cache coherency problem also arises when a non-caching device writes to a location in main memory which has been cached by another device.
As known in the art, some systems maintain cache coherency. For some of the methods used to maintain cache coherency, it is necessary to introduce "wait" states when data in the data cache is accessed sequentially by either the local processor or main memory. Wait states are necessary to ensure a sufficient amount of time exists to maintain cache coherency.
An alternative to wait states is to utilize two data cache memories, one for the local processor and one for main memory. Using two data cache memories, however, results in an area penalty, since an extra memory array is required.
Therefore, it would be desirable to provide a method and system for improved transferring of data to or from a cache memory.